Data to be sent by the I2C Master Block. The format is UFix_40_0, but it contains 5 data of 8 bits each as required by I2C protocol. From MSB to LSB → Data1, Data2, Data3, Data4, Data5.

Number of 8 bits data to be sent by the master in one command, without a stop or repeating the address. Can go from 1 to 5. If you send only a “DataLen” of 3, the master will only send the 24 LSB of the “Data_In” (in three separate 8 bit frames), while ignoring the 16 MSB. Format UFix_3_0.

Specifies whether the slave address is written on 7 or 10 bits. If 10 bits mode is selected (“10Bits_AddressMode” = 1), the master will send the address in two frames, separated by an ACK Bit :

• First Frame : ‘11110’ (sequence to identify the 10 bits address mode) && Slave_Addr[9:8]

• Second Frame : Slave_Addr[7:0]

If “10Bits_AddressMode” = 0, only the 7 LSB of the address (Slave_Addr[6:0]) will be used.

The format is UFix_1_0.

The address of the slave which the Master addresses.

The format is UFix_10_0 but all might not be used depending on the value of the “10Bits_AddressMode”.

This input specifies whether the master should keep on sending the command even though it hasn’t received an expected Ack bit from the slave (“Ommit_Ack” = 1) or it should stop the communication (“Ommit_Ack” = 0).

The format is UFix_1_0.

This input specifies whether the Master shall perform a Read (“Read_Write” = 0) or a Write (“Read_Write” = 1).

The format is UFix_1_0.

This input is the first 8 bits data frame sent after the Slave Address and before the “Data_In” data by the Master. This data frame is usually used by the slave to identify which register address to write the following data to in case of a write, or which register address to read the data from in case of a read. This is a particular application, but any slave can interpreter this data frame according to its implementation.

The format is UFix_8_0.

This input tells whether the Master should send a stop frame (“Repeated_Start” = 0) or not (“Repeated_Start” = 1) at the end of the transmission. This is in order to keep the exclusivity of the Slave bus, in a multi-master communication, because if the Master sends a stop frame, any other master that sends a command first can access the Slave bus.

The format is UFix_1_0.

When activated, this input creates an I2C transaction with the current inputs of the block.

The format is UFix_1_0.

Specifies whether the Master allows the Slave to stretch its clock.

The format is UFix_1_0.

The I2C clock line coming from the slave.

The format is UFix_1_0.

The I2C data line coming from the slave.

The format is UFix_1_0.

This input specifies whether the master is enabled or not.

The format is UFix_1_0.

This output specifies that the outputs “Addr_Out” and “Data_Out” are currently outputting valid data.

The format is UFix_1_0.

The address from which the Master is reading from the Slave.

The format is UFix_8_0.

The data read from the Slave.

The format is UFix_8_0.

This output specifies whether the Master is currently performing a transaction.

The format is UFix_1_0.

The I2C clock line of the Master.

The format is UFix_1_0.

The I2C data line of the Master.

The format is UFix_1_0.

The I2C Tri-Sate buffer of the Master, indicates whether it’s the master’s turn to communicate, useful for the open-drain logic of the serial bus (look at the example model I2C_RTXSG in %RTXSG_ROOT%/Examples/Features/I2C).
The format is UFix_1_0.

N/A

N/A

N/A

YES