Block

Mask

Description

This block represents the input link of the FPGA through the SignalWire bus. Data may be coming from the PC target or from a previous FPGA in a multiple chip design. Sixteen input ports are provided to the user for data samples and control signal transfers.

One of the functions of this block is to perform data conversion from uint32 to the System Generator UFix33_0 data format. It is up to the user to extract the desired data out of the 32 least significant bits and to reinterpret these bits to the desired format (signed or unsigned with or without binary point).

This block is linked to the inputs of the OpCtrl Reconfigurable IO block found in the RT-LAB CPU model: port #1 of the OpCtrlReconfigurableIO corresponds to Cfg_IN1, port #2 to Cfg_IN2, etc.

Parameters

The buffering type allows a user to choose whether to synchronize incoming data, where only one data sample can be transferred per calculation step (data is synchronized with the model synchronization pulse) or to admit asynchronous mode where up to 250 samples can be transferred.

For example, a value of 010000000000101 in this field sets input ports 1 and 3 and 15 (MSB to LSB port representation) to asynchronous mode.

The "Provide Start Of Frame" parameter allows a user to choose whether or not a "Start Of Frame" pulse should be provided for the associated LoadIn port.

It should be noted that when the LoadIn port is configured in asynchronous mode, the first DataValid (bit 33 of LoadIN) will follow the Start Of Frame on subsequent clock cycle. When configure in synchronous mode, Start Of Frame and DataValid are high on the same clock cycle.

Inputs

Cfg_IN	This is a vector of 32 uint32 type signals. Each of these signals represents an input port on the OpCtrlReconfigurableIO block of the RT-LAB CPU model.

Outputs

Cfg_IN{1,...,32}	Each of those ports is of UFix33_0 format where the first 32 bits represent the data and bit 33 (most significant bit) is the valid signal indicating when the information is updated. When in synchronous mode (default) the valid bit is in sync with the MSync or model calculation step (active high for 10 ns). In asynchronous or in burst mode, this bit is active on arrival of the data.
SofIN{1,...,32}	Each of those port is a one-bit single cycle high pulse indicating a start of frame.

Characteristics and Limitations

This block has no special characteristics.

Direct Feedthrough	NO
Discrete sample time	NO
XHP support	N/A
Work offline	YES