Block

Mask

Description

Implements a phase-domain permanent-magnet machine model with full fault capability (including open-terminal faults) in an RT-XSG model. The model is equivalent to a Park model.

The models are implemented using per-unit scaling on most quantities using a phase-domain model with open-stator fault capability. The model has a latency of 20 FPGA clock cycles.

Parameters

This block has no parameter.

Inputs

Vabc	Must be connected to a bus containing the Phase A, B and C terminal voltages (named 'Va', 'Vb' and 'Vc', respectively), in PU, and in the Fix18_15 format.
L	Must be connected to a bus containing the (1,1), (2,1), (1,2) and (2,2) components of the inversed of the reduced 2x2 inductance matrix (named L1, L2, L3, and L4, respectively), in PU and in the Fix18_15 format.
High_Impedance	Logical signals to set individual stator phase in open state (high impedance). When set to 1, the stator impedance is set to the value provided in the Resistances input.
Parameters	This port contains various parameters used to configure the motor model. This port must be connected to a bus containing the following signals: Ra: Normal phase A resistance, in PU and in the Fix24_18 format. Rb: Normal phase B resistance, in PU and in the Fix24_18 format. Rc: Normal phase C resistance, in PU and in the Fix24_18 format. Hi_Imp: High-impedance value of the permanent-magnet machine, used when High_Impedance is active on any of the three phases, in PUs and in the UFix24_18 format. IntCTE: This signal provides the model integration constant. It must be in the UFix47_47 format.
Theta	The electrical angle of the rotor in [0 1] format. The rotor direct axis is located under phase A for an angle of 0. Equivalently, the maximum BackEMF (for positive speed) is reached at a rotor angle of 0.75 (3π/4), i.e. a quarter of an electrical period before the rotor reaches the A phase position.
we_pu	Rotor electrical speed, in PUs and in the F18_15 format.
RAMData	This port is used to initialize the Back-EMF table from the EMF.mat block located in the CPU. This table is modified according to the motor type and parameters. This port shout receives data from the RT-LAB subsystem via a DataIN block port.

Outputs

Iabc	Machine current for phase A, B, and C, in the Fix18_15 format (a bus with signals named Ia, Ib and Ic, respectively).
Vind_ABC	Back-EMF induced voltage for phase A, B, and C, in the Fix18_15 format (a bus with signals named Va, Vb and Vc, respectively).
V_neutral	Stator neutral point voltage, in the Fix18_15 format.
LambdaABC	Flux induced by the motor magnet, for phase A, B, and C, in PUs and in the Fix18_15 format (a bus with signals named LambdaA, LambdaB and LambdaC, respectively).

Characteristics and Limitations

This block requires a specific license for FPGA configuration file generation and during runtime.

Direct Feedthrough	N/A
Discrete sample time	N/A
XHP support	N/A
Work offline	NO

RT-XSG Documentation

Permanent Magnet Machine