Block

Mask

Description

The Quadrature Encoder block generates the A, B and Z signals of a quadrature encoder module with a specific number of pulses per turn according to an input angle or speed. Outputs A and B have a specific phase difference that enables a decoder to retrieve the modulated signal angle and speed at any time.

Parameters

Encoding configuration	This parameter is used to specify the encoding pattern (according to the encoder specification, the A pulse may come before or after the B pulse, for a positive speed). The user chooses between A leads B or B leads A, which applies to a positive speed (the leading channel is interchanged for a negative speed). He can also choose from the input port. The first diagram shows in the figure below represents the choice of A lead B (positive speed). The second diagram represents the choice of B lead A (positive speed).
Polarity	Used to specify a polarity of A and B signals. The user chooses between Active-high or Active-Low or from the input port.
Provide resolution as	Two options are available. When As input port is selected, a new input appears in the block and the user provide this parameter from the CPU model. When A block parameter is selected, a new field Number of pulses per turn appears.This parameter indicate the number of A/B pulses per turn (i.e. between two consecutive Z pulses if the rotation direction does not change).
Provide input as	This parameter enables the designer to select the input type of the block. The input can provide the encoder angle, given as a turn ratio between 0 and 1. The input can also be given as a step, proportional to the machine speed, expressed as a turn ratio per FPGA clock cycle. Note that this step is likely to be very small, and thus to require many bits after the binary point. The recommended format is Fix42_42, giving a wide range for the device speed. Feeding the block with the speed instead of the angle facilitates the use of the block when it is connected to RT-LAB signals, as the angle is generated directly inside the block, and is updated at every FPGA clock cycle.
Synchronization pulse width	This parameter sets the width of the Z output pulse (the length of the active pulse) relatively to the duration of one cycle of the A and B signals.

Inputs

Angle	The angle modulating the quadrature encoder. The angle must be provided as a turn ratio, in the range [0,1]. The presence of this input and of the Step input are mutually exclusive, according to the mask parameters.
Step	The speed of the angle generator located inside the block. The speed must be provided as a turn ratio per FPGA clock cycle, in the range [-0.5,0.5]. This value is likely to be very small. Thus, the recommended format is Fix42_42, which provides a convenient range for the Step value. The presence of this input and of the Angle input are mutually exclusive, according to the mask parameters.
rst	If the block uses the Step input to generate its output, this input is used to reset the angle of the device to 0.

Outputs

A	The A channel. The number of A pulses per turn is specified as a block parameter.
B	The B channel. The number of B pulses per turn is specified as a block parameter and is equal to the number of A pulses.
Z	The Z channel. One Z pulse occurs per turn, when the angle is close to zero. The width of the Z pulse is set by the Synchronization pulse width parameter.

Characteristics and Limitations

This block has no special characteristics. Figure 1 presents an example of its behavior for positive speed.

Direct Feedthrough	N/A
Discrete sample time	N/A
XHP support	N/A
Work offline	YES

RT-XSG Documentation

Quad Encoder