Block

Mask

Description

This block generates a synchronization pulse train with the specified period. The width of the pulse equals the FPGA board clock period, during which its output value is the unsigned integer '1'. Otherwise it is the unsigned integer '0'.

Parameters

This block has no parameters.

Inputs

Cfg_in	This signal retrieves the data form LoadInPort. The first data is the offset of the first analog acquisition. The second data is the period of acquisition. These two data are expressed in ticks of FPGA clock.
SoF	This signal is the start of frame of LoadIn port uses to retrieve data from CPU. This input is useful to synchronize data reception from CPU.

Outputs

This block has no outputs.

Characteristics and Limitations

This Block has no specific characteristics or limitations.

Direct Feedthrough	NO
Discrete sample time	NO
XHP support	N/A
Work offline	NO

RT-XSG Documentation

RCP - Ain Sync Generator