Block

Mask

Description

This block performs the signal conversion and rescaling to an integer signal containing all bits representing the data in the FPGA, in an Unsigned or Signed fixed-point numerical format.

Parameters

Type of numerical format	Used to specify signal shall be interpreted as Signed or Unsigned.
Total number of bits	Used to specify the total number of bits of the fixed-point format.
Number of fractional bits	Used to specify the number of fractional bits of the fixed-point format (the number of bits on the right-hand side of the binary point). This parameter sets the resolution of the signal.

Inputs

DBL	This signal is the floating-point signal, in the double format.

Outputs

INT	This signal is the output signal, in the fixed-point numerical format. This signal is in the Simulink uint32 format, and the effective signal corresponds to the LSBs of the integer, with the width specified in the appropriate block parameter.

Characteristics and Limitations

The total number of bits of the output signal is limited to 32 bits.

Direct Feedthrough	N/A
Discrete sample time	N/A
XHP support	N/A
Work offline	YES

RT-XSG Documentation

Rescale to Fixed Point Format