Block

Mask

Description

This block generates output resolver signals: modulated sine and cosine, sine and cosine envelop and motor angle.

These signals can then be sent to an analog output module (see OP5330 DAC IFblock) and be sent to an external device with fast-sampling precision.

Generated output signals

Parameters

Reset Angle (rad)	Used to reset angle when one complete round is done by the rotor. It also determines the initial angle of the rotor. This parameter must be between 0 and 2π.
Angle Resolution(bits width)	Shows the depth of the SinCos table. Currently set at 14 bits deep (cannot be changed).
Sin-Cos table width (power of 2)	Determines the width of Sin table used for internal carrier signal build. Currently set at 18 bits width (cannot be changed).

Inputs

CarrierSelect	Chooses between the internal carrier and external carrier coming from Analog In module. Its format is UFix1_0.
CarrierFreqIntegrationFactor	Internal carrier frequency coming from the CPU model. Its format is UFix32_24. This input is a factor of the real value. The value at the input is the carrier frequency multiplied by 10x10^-9 (tsfpga) and 2^18 (integrator output maximum value).
CarrierAmp	Internal carrier amplitude coming from the CPU model. Its format is Fix16_11.
SinAmp	Amplitude (coming from CPU model) of the generated modulated sine signal. Its format is UFix16_11.
SinBias	Bias (coming from CPU model) of the generated modulated sine signal. Its format is Fix16_11.
CosAmp	Amplitude (coming from CPU model) of the generated modulated cosine signal. Its format is UFix16_11.
CosBias	Bias (coming from CPU model) of the generated modulated cosine signal. Its format is Fix16_11.
SpeedIntegrationFactor	Speed coming from the CPU model. Its format is Fix32_25. This input is a factor of the real value. The value at the input is the speed multiplied by 10x10^-9 (tsfpga) and 2^18 (integrator output maximum value).
ExtCarrier	External carrier coming from Analog In module. Its format is Fix16_10.
Alpha	Cosine of the phasing between the modulated sine signal and modulated cosine signal. This input comes from the CPU model. Its format is Fix18_16.
Beta	Sine of the phasing between the modulated sine signal and modulated cosine signal. This input comes from the CPU model. Its format is Fix18_16.

Note about the Integration Factors: The Integration Factors are used to generate an angle of the motor's rotor. The method of calculation is based on a single addition block loopback on itself. The natural overflow from the addition of free runs produces a sawtooth wave between 0 and (2^18)-1. This is why you must factor the carrier frequency and speed.

Outputs

Carrier	Carrier (either internal or external) used for modulated signals generation is the internal carrier frequency coming from CPU model. Its format is Fix16_11.
SinRES	Resolver modulated sine. Its format is Fix16_11.
CosRES	Resolver modulated cosine. Its format is Fix16_11.
Theta	Equivalent normalized speed angle. Its format is UFix18_18.
Sin	Resolver sine envelope. Its format is Fix16_11.
Cos	Resolver cosine envelope. Its format is Fix16_11.

Characteristics and Limitations

This block has no specific characteristics or limitations.

RT-XSG Documentation

Resolver Out