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1 Block
2 Description
3 Parameters
4 Inputs
5 Outputs
6 Characteristics and Limitations

Block

Description

The I2C Slave block allows to implement an I2C compliant interface.

Parameters

No configurable parameters.

Inputs

Read_Valid	Signal telling the inputs “Read_Data” are valid and ready to be used to respond to a read request by the Master. The format is UFix_1_0.
Read_Data	Data to be sent back to the master through the I2C communication when “Read_Valid” input is active. The format is UFix_8_0.
Device_Address	The address of the device to emulate. Address is encoded using this logic : The format is UFix_16_0.
Clk_Stretch_Enable	This input specifies if the clock stretching is enabled. This signal consists of 4 bits, each enabling the clock stretching for a specific part of the transaction. bit 0: Clock stretching enabled for the “device address” part of the transaction. bit 1: Clock stretching enabled for the “register address” part of the transaction. bit 2: Clock stretching enabled when sending data back to the master. bit 3: Clock stretching enabled when receiving data from the master. If the value of one of those bits is 1 (HIGH) then a clock stretching time of the value of the input “Clk_Stretch_Time” will be applied at the respective Ack bit described previously. The format is UFix_4_0 .
Clk_Stretch_Time	Time, in number of FPGA clock cycles to be applied for the clock stretching. The format is UFix_25_0.
Master_SCL	The I2C clock line coming from the Master. The format is UFix_1_0.
Master_SDA	The I2C data line coming from the Master. The format is UFix_1_0.
Slave_Enable	This input specifies whether the Slave is enabled or not. The format is UFix_1_0.

Outputs

Write_Enable_Out	This output specifies that the outputs “Write_Addr_Out” and “Write_Data_Out” are currently outputting valid data. The format is UFix_1_0.
Write_Addr_Out	The address to which the Master is writing to. The format is UFix_8_0.
Write_Data_Out	The data the Master is writing. The format is UFix_8_0.
Read_Enable_Out	This output specifies that the outputs “Read_Addr_Out” is currently outputting valid data. The format is UFix_1_0.
Read_Addr_Out	The address from which the Master wants to read from. The format is UFix_8_0.
Slave_SCL	The I2C clock line of the Slave, only useful for clock stretching, since the Master provides the clock. The format is UFix_1_0.
Slave_SDA	The I2C data line of the Slave. The format is UFix_1_0.

Characteristics and Limitations

Needs special hardware that transforms the 4 communication lines (SDA in/out, SCL in/out) in serial 2 lines to communicate with an external master, it will still work with the RT-XSG I2C master Block.
Maximum frequency is 1 MHz.
Only supports the combined format (a write with a length of 0 following a read) to perform a read operation.

Direct Feedthrough	N/A
Discrete sample time	N/A
XHP support	N/A
Work offline	YES