This parameter allows the user to configure the block as a Master, Slave, or Master/Slave. When Configured as Master/Slave, an input port Mode is made available for the user to configure the Block dynamically.

This parameter is made available only when the Block is configured as Master or Master/Slave. It allows users to specify the number of slave devices attached to the master.

This parameter allows the user to specify the frequency via a block parameter or via an input of the block.

This entry is made available if the "Provide Baud Rate" parameter is selected as "As Block Parameter".

The user specifies the frequency by providing the System Clock divider value (e.g. System clock 100MHz, SCK 10MHz, Baud rate 100MHz/10MHz). 16 bits.

The clock phase and polarity can be modified for SPI data transfers. To remain flexible enough to work with many implementations of the I/O logic, the SPI Interface can toggle its serial clock phase and polarity.

• The parameters that control this are CPHA (for Clock PHAse), and TX Polarity (CPOL for Clock POLarity).

• The CPOL parameter defines the base state of the clock at the beginning of each packet, high or low.

• The CPHA parameter defines when data is loaded into the slave device's output register to be sampled by the host.

• If CPHA = "0", data is valid on the first SCK edge (rising or falling) after Slave Select has asserted. If CPHA = "1", data is valid on the second SCK edge (rising or falling) after Slave Select has asserted.

The figure above shows the timing diagram for an SPI data transfer when the clock phase, CPHA, is set to "0". The waveform is shown for both positive and negative clock polarities of SCK.

The SCK signal remains inactive for the first half of the first SCK cycle (SCK Cycle 1). In this transfer format, the falling edge of Slave Select indicates the beginning of a data transfer. Therefore, the Slave Select line must be negated and reasserted between each successive serial data transfer.

The figure above shows the timing diagram for an SPI transfer when the clock phase, CPHA, is set to "1". The waveform is shown for both positive and negative clock polarities of SCK.

The first SCK cycle begins with an edge on the SCK line from its inactive to its active level. The first edge of SCK indicates the start of the data transfer in this format.

In accordance with these rules, the parameters TX and RX Polarity should be set according to this table to set the SPI block in the desired SPI mode:

This parameter sets the polarity of the Slave Select signals. If the user selects the option "As an input port", the polarity can be dynamically through the Block input port.

This parameter sets the width of the data. If the user selects the option "As an input port", the width can be dynamically through the Block input port.

This parameter allows the user to specify the Delay Compensation Factor via a block parameter or via an input of the block.

This entry is made available if the "Provide Delay Compensation" parameter is selected as "As Block Parameter". The user specifies the Delay value between 0 and 63.

This signal permits setting the mode of operation of the SPI Interface Block as Master or Slave.

This port is made available only if the developer selects the option "Master/Slave" in the mask parameters.

This signal permits the setting of the operating frequency of the SPI clock.

This port is made available only if the developer selects the option "As Block Input" in the mask parameters.

This signal permits setting the clock phase to select one of two fundamentally different transfer formats.

This port is made available only if the developer selects the option "As an input port" in the mask parameters.

This signal permits the selection of the polarity of the transmitting data (transmit). It usually corresponds to the Clock Polarity (CPOL).

This port is made available only if the developer selects the option "As an input port" in the mask parameters.

This signal permits the selection of the polarity of the receiving data (latch).

This port is made available only if the developer selects the option "As an input port" in the mask parameters.

This signal permits the selection of the polarity of the Slave Select signal.

This port is made available only if the developer selects the option "As an input port" in the mask parameters.

This signal permits the setting of the width of the data.

This port is made available only if the developer selects the option "As an input port" in the mask parameters.

This signal permits the setting of the Delay Compensation. 

This port is made available only if the developer selects the option "As Block Input" in the mask parameters.

Port representing the data to be transmitted serially by the Block. The SPI block can accept up to 28 DWORDs in one calculation step, but care should be taken to avoid overflowing the SPI internal FIFOs by monitoring the status flags.

Packets sent to the block should conform to the following formatting:

The first DWORD should have these fields:

• Bit 31:28 Allow selecting the slave number to which data will be transmitted to when configured as master. This field is not used when configured as a slave.

• Bit 27:0 Allow specifying the amount of data that will be sent to the SPI block. Each bit represents one piece of data.

The following DWORDs are the SPI data to be sent by starting with the least significant group. Per example, sending data1="EF00GH00" and data2="ABCD0000" will result with the message "ABCD0000EF00GH00", so the SPI stream will start with "1010" and not "1110".

Slave SPI clock

This port is made available only if the Block is configured as Slave or Master/Slave

Slave input data port

This port is made available only if the Block is configured as Slave or Master/Slave

Master input data port

This port is made available only if the Block is configured as Master or Master/Slave

Slave "Slave Select" input port

This port is made available only if the Block is configured as Slave or Master/Slave

SPI Enable input

This active high input enables the normal operation of the SPI. During Configuration (e.g. Changing Frequency), this input must be in the low state

This signal holds the receiving data

This signal holds the timestamp of the receiving data

This port holds the status of the SPI interface Block

Prior to RT-XSG v3.4.0

• Bit 6:0 Represent the amount of Data in the Transmitting FIFO

• Bit 13:7 Represent the amount of Data in the Receiving FIFO

• Bit 14 Indicate that the Transmitting FIFO is full

• Bit 15 Indicate that the Receiving FIFO is full

Starting with RT-XSG v3.4.0

• Bit 5:0 Represent the amount of Data in the Transmitting FIFO

• Bit 6 Indicate that the Transmitting FIFO is full

• Bit 14:7 Actual amount of bits left to be transmitted

• Bit 22:15 Actual amount of bits left to be received

Master SPI Serial Clock

Master SPI Serial data out

Slave SPI Serial data out

Slave Select lines

N/A

N/A

N/A

YES