Block

Mask

Description

This block adds a probe in the model. The probe connected here will enable acquisition of the signal(s) in input into the FPGA Acquisition system. Input can either be an isolated signal (up to 32 bits) or a FLWS stream of many signals.

Parameters

Input port is a: Signal/FLWS stream (Bus)	This parameter is used to specify the type of input signal of the block. Select "signal" if the input is directly connected to a System Generator signal, which should be an unsigned integer of up to 32 bits. For any other signal type, the input must be a FLWS stream.
Detect FLWS stream characteristics automatically	This parameter is visible only if the input signal format selected is "FLWS stream (Bus)". It enables RT-XSG to detect automatically the signal names and numerical formats in the FLWS stream connected in input to the block. Automatic detection is implemented only for RT-XSG library blocks, and this option should not be selected if the probe is put manually in the model by the user.
FLWS stream characteristics	This parameter is visible only if the input signal format selected is "FLWS stream (Bus)" and the probe FLWS stream characteristics are not set to be detected automatically. The parameter should be a JSON string representing the format of a list of signals in the FLSW stream. Refer to the Characteristics and limitations section for the formatting of this string.

Inputs

The input of this block should be either an isolated signal (up to 32 bits) or a FLWS stream in which the data is up to 32 bits.

Outputs

This block has no output.

Characteristics and Limitations

The JSON string described above has to follow a strict structure. It should represent a list in which each element have the following attributes:

"Name": A name for the signal (should be a string that is unique in the names within this list).
"Format": Numerical format, should be either "Unsigned", "Signed" or "Float".
"NbBits": Number of bits of the signal.
"BinPt" or "MantissaBits": For signed or unsigned, "BinPt" is the position of the binary point for the numerical format of the signal. For floats, "MantissaBits" is the number of bits of the mantissa for the numerical format of the signal.
"ByteOffset": Byte offset of the least significant bit of the signal, from the beginning of the stream. Is incremented by 4 for each increment of the index of the 32-bit elements within the FLWS stream, plus one for each complete byte within that element.
"BitOffset": Any bit offset of the least significant bit of the signal, from the beginning of the stream, not included in the byte offset described above. The value of the bit offset should be between 0 and 7.
"Selected": Default state of the signal selection in the CPU application of the FPGA Acquisition feature. Recommended is false.

Here is an example for a FLWS stream containing two 32-bit elements. The first element is a floating-point signal called "Current_measurement", in single floating-point format, and the second is the concatenation of two angle signals of 16 bits each, theta_1 and theta_2, each with format Ufix_16_16. The string has been formatted for readability, but can be included without the line breaks in the mask parameter.

          [
            {
              "Name": "Current_measurement",
              "Format": "Float",
              "NbBits": "32",
              "MantissaBits": "24",
              "ByteOffset": "0",
              "BitOffset": "0",
              "Selected": false
            },
            {
              "Name": "theta_1",
              "Format": "Unsigned",
              "NbBits": "16",
              "BinPt": "16",
              "ByteOffset": "4",
              "BitOffset": "0",
              "Selected": false
            },
            {
              "Name": "theta_2",
              "Format": "Unsigned",
              "NbBits": "16",
              "BinPt": "16",
              "ByteOffset": "6",
              "BitOffset": "0",
              "Selected": false
            }
          ]

Direct Feedthrough	N/A
Discrete sample time	N/A
XHP support	N/A
Work offline	NO

RT-XSG Documentation

FPGA Acquisition Probe