The blocks of this library are used for describing the properties and IO interfaces of RT-XSG blocks. These blocks are used in the context of the RT-XSG Modules project for automatic generation of IOCONF firmware description files. Creating RT-XSG Modules instrumented blocks contextualizes them to be added in the IOCONF firmware description file alongside other RT-XSG Module compliant blocks. The library is organized in 3 types of blocks, the property block, the input blocks and the outputs blocks.

Preface

To create RT-XSG Module compliant feature blocks that will be recognized by the automatic IOCONF generation tool, the resulting block NEEDS to be saved inside a Simulink Library file! After following the steps below to create your RT-XSG Module feature block, make sure to save it in a Simulink library file and import that library block into your model. Do not try to use Module Properties or Module IO blocks directly in your model.

Making a RT-XSG feature block using Description Module Blocks

In an effort to standardize the creation of RT-XSG feature blocks and simplify the generation of a COMPLETE model description, the module description blocks were created to help FPGA model designers create easy to connect custom features. The goal of the feature is to provide clear and simple interface blocks for the user to encapsulate his FPGA feature block with description, input and output blocks.

Open

To create a RT-XSG feature block that will be recognized by the Automatic ioconf file generation process, it minimally needs to have a RT-XSG Module Properties Block. With a Module Properties block added to the feature block, it will be registered and added to the list of feature blocks of the RT-XSG model in the generated ioconf file.

To give the RT-XSG feature block the ability to connect to other feature blocks within the model (i.e. DataIn, LoadIn, DataOut, eHS Solver, Analog Output Mapping Rescaling, etc), RT-XSG Module Inputs & Outputs need to be added on the desired input or output ports of the block. Every INPUT port instrumented with a RT-XSG Module Input Port block will, if it finds a complimentary RT-XSG Output Module Port connected to it in the model, register and add that connection to the list of block connections of the RT-XSG model in the generated ioconf file. A connection between two blocks in the model is described as:

From Source Block (Module Properties) with Source Port (Module Output Port) to Destination Block (Module Properties) with Destination Port (Module Input Port).

The input blocks receive FLWS signals and the output blocks output FLWS signals. They respectively can deserialize and serialize data going to and from the logic unit meaning all feature block propagate their data using the FLWS protocol but can internally use deserialized data.