Blocks

RT-XSG Vivado Debug Core

RT-XSG Vivado Debug Port

Masks

Description

The ILA blocks allow cycle-accurate probing of arbitrary signals in the RT-XSG models.

See Xilinx's documentation for details: Vivado Design Suite User Guide: Programming and Debugging (UG908) (PDF)

Common Flow

Add at least one RT-XSG Vivado ILA Core blocks to the design
Probe signals by adding one or more RT-XSG Vivado ILA Port blocks to the design
Generate a bitstream using the Opal-RT FPGA Synthesis Manager block
Flash the bitstream by loading an RT-LAB model or manually with Vivado
Open the Vivado ILA by clicking on the button in the RT-XSG ILA Debug Core block

Notes

Each debug core can have its own capture and trigger settings
Each debug port is associated with one debug core
Each debug port or core can be enabled & disabled
Datatypes and port width are detected automatically
Checks for the existence of debugging cores are performed
All System Generator datatypes can be probed
Simulink Busses are currently not supported

Parameters

Each ILA Debug Core block has the following parameters which mostly are passed directly to Vivado:

Each ILA Debug Port block has the following parameters:
Enabled	Allows disabling the debug core including all referenced debug ports completely. No FPGA resources are used in this case.
Depth (C_DATA_DEPTH)	The maximum number of data samples that can be stored by the ILA core. Increasing this value causes more block RAM to be consumed by the ILA core and can adversely affect design performance.
Advanced trigger (C_ADV_TRIGGER)	Enables the advanced trigger mode of the ILA core. Refer to Chapter 9 of Xilinx' UG908 for more details on this feature.
Input pipe stages (C_INPUT_PIPE_STAGES)	Enables extra levels of pipe stages (for example, flip-flop registers) on the PROBE inputs of the ILA core. This feature can be used to improve timing performance of your design by allowing the Vivado tools to place the ILA core away from critical sections of the design.
Match units per probe (C_ALL_PROBE_SAME_MU_CNT)	The number of comparators (or match units) per PROBE input of the ILA core. The number of comparators that are required depends on the settings of the C_ADV_TRIGGER and C_EN_STRG_QUAL properties: If C_ADV_TRIGGER is false and C_EN_STRG_QUAL is false, then set to 1. If C_ADV_TRIGGER is false and C_EN_STRG_QUAL is true, then set to 2. If C_ADV_TRIGGER is true and C_EN_STRG_QUAL is false, then set to 1 through 4 (4 is recommended in this case). If C_ADV_TRIGGER is true and C_EN_STRG_QUAL is true, then set to 2 through 4 (4 is recommended in this case). IMPORTANT: if you do not follow the guidelines above, you may encounter an error during operation.
Enabled	Allows disabling a single debug port only.
Debug Core	The block name of the debug core to which this port will be attached.
Type (PROBE_TYPE)	The type of this probe: DATA_AND_TRIGGER: This probe port can be used as trigger and captures data. DATA: This probe port only captures data but can not be used for triggering the ILA. TRIGGER: This probe port only can trigger the ILA. This saves BRAM resources as no data will be captured in Block RAMS.

Inputs

The ILA Debug Port block has a single input which has to be connected to the signal which should be captured. Currently, all System Generator data types, with the exception of Simulink busses, are supported. Data type and width of the signal is detected automatically.

Outputs

These blocks have no outputs.

Characteristics and Limitations

This block has no special characteristics.

Direct Feedthrough	N/A
Discrete sample time	N/A
XHP support	N/A
Work offline	NO

RT-XSG Documentation

Vivado ILA Blocks