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Using eHS with Schematic Editor
- Sylvain Ménard
Owned by Sylvain Ménard
This page focuses on our main workflow based on our brand new Schematic Editor.
- Quick start guide : Run a model on FPGA using the Schematic Editor
- Block Library
- Schematic Editor Block Library
- SPS Block Library
- eHS Variable Load - efsVariableLoad
- Generic Machines - efsCpuGenericMachines
- Resolver Encoder Sensors - efs_ResolverEncoderSensors
- Variable Load Parameter - efsCpuVariableLoadParameterCfg
- Variable Load Configurator - efsCpuVariableLoadCfg
- 24-Phase H-Bridge Inverter - efs24PhHBridgeInverter
- 24-Phase Hysteresis Controller - efs24PhHystCtrl
- 24-Phase Permanent-Magnet Synchronous Machine - efs24PhMotor
- Analog Input Differential Rescaling Controller - efs_cpuAIDR
- Analog Out Mapping Rescaling V2 Control Panel - efs_cpuAOMRV2ControlPanel
- Chassis Selection - efsChassisSelection
- Analog Out Mapping and Adjustments - efs_cpuAOut_Mapping
- CPU stubline configuration - efsCpuEhsStubline
- Digital Output Mapping - efsCpuDigitalOutputMapping
- Dual Angle Sensors with faults CPU - efs_cpuAngleSensorsWFaults
- Dual eHS - efs_Dual_eHS
- Dual PMSM Motors SH v1 - efs_cpuPMSM_SH
- Dual PMSM Motors SH Advanced Command - efs_cpuAdvancedCommandSH
- Dual PMSM Motors SH v2 - efs_cpuPMSM_SHv2
- Dual PMSM Motors VDQ Advanced Command - efs_cpuAdvancedCommand
- Dual PMSM Motors VDQ - efs_cpuPMSM_VDQ
- Dual Vabc Test Sources Block - efs_cpuDualVabcTestSources
- eHS Data Convert for SFP - efs_ehs_sfp
- eHS Gen3 SPS DEPRECATED - efs_eHSGen3
- eHS Offline simulation - efs_eHS_Offline
- eHS Solver License Class - efs_FindLicenseClass
- eHSx32 for OP4200 - efs_eHSOP4200
- eHSx64 Command block - efs_eHSx64
- Foster thermal network - efsFosterNetwork
- FPGA 2 inputs dot product configuration block - efsCpuTwoInputDotProduct
- FPGA 64-to-64 Interconnect Controller Block - efs_cpuInterconnect64
- FPGA 64-to-64 Interconnect Controller Panel - efs_cpuInterconnect64ControlPanel
- FPGA Discrete 1-Phase PLL - efs_cpuOnePhasePLL
- FPGA First-Order Filter - efs_cpuFirstOrderFilter
- FPGA PI Controller - efs_cpuPI
- FPGA PID Controller - efs_cpuPID
- FPGA Second-Order Filter - efs_cpuSecondOrderFilter
- Generic High Speed Communication Block for eHS - efs_inter_ehs_sfp
- Generic Machines Brushless DC Machine BLDC Model - efsCpuGenericMachinesBldcModel
- Generic Machines Induction Machine Model - efsCpuGenericMachinesImModel
- Generic Machines Permanent Magnet Synchronous Machine PMSM Model - efsCpuGenericMachinesPmsmModel
- Generic Machines Synchronous Machine Model - efsCpuGenericMachinesSmModel
- Induction Machine Command - efs_cpuIM
- Inverter Solver with Boost Command - efs_cpuInverter_wboost
- Left side / Right side stubline - efsEhsStubline
- Resolver Encoder Mapping - efs_ResolverEncoderMapping
- RT-XSG Scope Series - efsCpuScopeSeries
- RT-XSG Scope Series Control - efsCpuScopeSeriesCtrl
- Selectable Digital Input - efs_cpuSelectableDI
- Selectable Digital Output - efs_cpuSelectableDO
- Machine Interface Parallel to Parallel and Serial to Parallel Wrapper - efs_cpuP2PS2P_Wrapper
- Solver Time Step Counter - efs_ehsTimeStepCounter
- Switched-Reluctance Motor - efs_cpuSRM
- Switched Reluctance Motor Hysteresis Controller - efs_cpuSrmHysteresisController
- Switching function configuration - efsCpuSwitchingFunctionCfg
- Thermal losses feature - efs_thermal_losses
- Time-multiplexed Capacitor Differential Equation Solver Configuration - efs_cpuTMCDE
- Vabc Test Source - efs_cpuVabcTestSources
- eHS Frequency dependent line block - efsEhsFrequencyDependent
- Parallel to Parallel Interface - efs_cpuP2P
- Serial to Parallel Interface - efs_cpuS2P
- Conf File writing Conventions
- Analog Out Mapping Rescaling V1 Control Panel - efs_cpuAOMRControlPanel
- CPU Power Measurement Configuration - efs_Monitoring_cpuPowerBlock
- eHS Gen4 SPS - efs_eHSgen4
- Half Line - efsEhsHalfLine
- XSG Block library
- Analog Output Mapping and Rescaling Block V2 - efs_xsg4AOut_MappingV2
- FLWS Filter - efs_xsgFLWS_Filter
- 1D-LookUp Table for XSG - efsXsg1DLut
- Variable state space block - efsXsgVariableLoad
- SFP Mapping and Communication Block - efs_sfp_mapping_communication
- FLWS Mapping and Rescaling Block - efs_xsgFLWS_Mapping
- Analog Output Mapping and Rescaling Block V2 - efs_xsgAOut_MappingV2
- Angle Sensor Emulator block - efs_xsgAngleSensors
- Capacitor Differential Equation Solver - efs_xsgCapacitor
- Digital Output Mapping - efsXsgDigitalOutputMapping
- Discrete 1-Phase PLL - efs_xsgPLL
- Discrete First-Order Filter Single floating-point - efs_xsgFirstOrderFilter
- Discrete Second-Order Filter - efs_xsgSecondOrderFilter
- Dual PMSM Model - efs_xsgDualPmsm
- Dual PMSM SH Solver block - efs_xsgDualPMSMSH
- Dual PMSM VDQ Solver block - efs_xsgDualPMSMVDQ
- Dual Resolver Encoder - efsXsgDualResolverEncoder
- eHS solver for RT-XSG block - efs_eHS_Fpga
- eHS solver for RT-XSG block - efs_eHSGen3_Fpga
- eHS to Machines Mapping Interface - efs_xsgEhsMachineMapping
- FPGA 64-to-64 Interconnect Block - efs_xsgInterconnect64
- Analog Output Mapping and Rescaling Block - efs_xsgAOut_Mapping
- Analog Input Differential Rescaling Block - efs_xsgAIDR
- eHS Gen3s Solver for XSG - efs_xsgeHSGen3s
- eHS Gen4 Solver for XSG - efs_xsgeHSGen4
- Frame-based LightWeight Serial FLWS Protocol for RT-XSG models - efs_xsgFLWS
- Frequency dependent line - efsXsgFrequencyDependentLine
- Generic Machines block - efsXsgGenericMachine
- Induction Machine Solver block - efs_xsgInductionMachine
- Initialization Bus Address Filter - efsXsgInitAddrFilter
- Initialization Bus Data ID filter - efsXsgInitDataIdFilter
- Initialization Bus Param ID filter - efsXsgInitParamIdFilter
- Initialization Bus Ram Interface - efsXsgInitRamInterface
- Initialization Decoder - efsXsgInitDecoder
- Integrator - efs_xsgIntegrator
- Machine to eHS Interface 4x and 8x - efs_xsgMachineToEhsInterface
- Mechanical Model - efsXsgMechanicalModel
- Parallel to Parallel Interface - efs_xsgP2P
- PI Controller - efs_xsgPI
- PID Controller - efs_xsgPID
- Resolver Encoder block - efs_xsgResolverEncoder
- Route Mechanical Signals block - efs_xsgRouteMechanicalSignals
- RT-XSG Scope Block - efs_XSGScope
- RT-XSG Scope Series Block - efsXsgScopeSeries
- Saturable transformer - efsXsgXFOSat
- Selectable Digital Input - efs_xsgSelectableDI
- Selectable Digital Output - efs_xsgSelectableDO
- Serial to Parallel Interface - efs_xsgS2P
- Switched Reluctance Machine Solver block - efs_xsgSwitchedReluctanceMachine
- Time-multiplexed Capacitor Differential Equation Solver - efs_xsgTMCDE
- XSG thermal losses block - efsXsgThermalLosses
- FPGA Power Measurement - efs_Monitoring_fpgaPowerBlock
- FPGA Min Max Measurement Block - efs_Monitoring_fpgaMinMaxBlock
- SFP Data Type Convert for FLWS - efs_sfp_FLWS
- Custom Model XSG - efs_xsgCustomModel
- eHS Gen5 Solver for XSG - efs_xsgeHSGen5
- Digital Input Mapping Block - efs_xsgDigitalInputMapping
- Block Library
- Quick start guide : Update a model on FPGA using the Schematic Editor
- User Notifications from FPGA Power Electronic Toolbox
- How to integrate eHS Block
- FPGA-based Power Electronics Toolbox Produced Content
- How to tune eHS solver specific parameters
- eHS Gen4 solver
- eHS Gen5 solver
- How to choose discretization Method (Pade5 and Backward Euler)
- How to choose Solver Strategy (Smallest Time Step vs Lowest Latency)
- How to choose switch model (Pejovic and Quasi-supra)
- How to tune single switch parameters (Rdamp and Relax)
- How to tune two- and three-level switches (Prediction and Relaxation)
- How to integrate a firmware containing external models in the Schematic Editor
- How to tune machine snubbers
- eFPGASIM with RT-XSG Module - Rules and recommendations
- How to connect digital signals to eHS Gating Inputs with Schematic Editor
- How to create FPGA-based Custom Model compatible with Schematic Editor workflow
- How-to decouple eHS Gen5 circuit to improve minimum time step
- Discrepancies between single switches
- How to configure a generalized mutual inductance
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