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Resolver Input Subsection

Owned by Sylvain Ménard
Last updated: Mar 11, 2023

Block

Mask

Description

This block implements the standard way to package 2 Resolver In functionality blocks into the standardized I/O interface.

Parameters

This block has no parameters.

Inputs

Ch01_Ch00

Set of signals for Resolver_0.

Ch00: the resolver carrier signal coming from Analog Input (entire voltage range). This signal also called "exciter" should be the same (in phase, frequency, and amplitude) as the one sent to the resolver and used to modulate sine and cosine. Its format is Fix16_10.

Ch01: This input is the resolver modulated sine coming from Analog Input (entire voltage range). Its format is Fix16_10.

Ch03_Ch02

Set of signals for Resolver_0.

Ch02: This input is the resolver modulated cosine coming from Analog Input (entire voltage range). Its format is Fix16_10.

Ch03: Reserved.

Ch05_ch04

Set of signals for Resolver_1.

Ch04: the resolver carrier signal coming from Analog Input (entire voltage range). This signal also called "exciter" should be the same (in phase, frequency, and amplitude) as the one sent to the resolver and used to modulate sine and cosine. Its format is Fix16_10.

Ch05: This input is the resolver modulated sine coming from Analog Input (entire voltage range). Its format is Fix16_10.

Ch07_Ch06

Set of signals for Resolver_1.

Ch06: This input is the resolver modulated cosine coming from Analog Input (entire voltage range). Its format is Fix16_10.

Ch07: Reserved.

CarrierInvAmp_[X] where X=[0,1]This input from the CPU Model is the INVERSE of the resolver carrier amplitude in Volts. It is used internally for per-unit scaling. Its format is UFix16_12.
CarrierInOffset_[X] where X=[0,1]This input from the CPU Model is the offset of the resolver carrier in Volts. Its format is UFix16_10.
SineInInvAmp_[X] where X=[0,1]This input from the CPU Model is the INVERSE of the resolver sine amplitude in Volts. It is used internally for per-unit scaling. Its format is UFix16_12.
SineInOffset_[X] where X=[0,1]This input from the CPU Model is the offset of the resolver sine in Volts. Its format is UFix16_10.
CosineInvAmp_[X] where X=[0,1]This input from the CPU Model is the INVERSE of the resolver cosine amplitude in Volts. It is used internally for per-unit scaling. Its format is UFix16_12.
CosineInOffset_[X] where X=[0,1]This input from the CPU Model is the offset of the resolver cosine in Volts. Its format is UFix16_10.
w0*2*ksi_[X] where X=[0,1]This input from the CPU Model is the first parameter of the filter used to extract the position from the modulated signal. Its format is UFix24_4.
w0*2*dt_[X] where X=[0,1]This input from the CPU Model is the second parameter of the filter used to extract the position from the modulated signal. Its format is UFix24_9.
InternalCarrierDelay_[X] where X=[0,1]This input from the CPU Model is the delay of acquisition of modulated signals. This delay is taken into account when the carrier is generated internally. Its format is UFix11_0.
DemodulationCarrierSel_[X] where X=[0,1]This input coming from the CPU Model is used to select the carrier used for demodulation. When it is 0, the carrier specified by Carrier_in is used for demodulation; unless the carrier is generated internally by the Resolver In block. Its format is UFix1_0.
CarrierOutIntegrationFactor_[X] where X=[0,1]This input is the internal carrier frequency coming from the CPU model. Its format is UFix32_24. This input is a factor of the real value. The value at the input is the carrier frequency multiplied by 10x10^-9 (tsfpga) and 2^18 (integrator output maximum value).
CarrierOutAmp_[X] where X=[0,1]This input is the carrier amplitude in Volts coming from CPU model. It is used to step up the carrier amplitude to the voltage level required by the resolver "exciter". Its format is UFix16_11.
CarrierOutOffset_[X] where X=[0,1]This input is the carrier offset in Volts coming from CPU model. It is used to shift the carrier to the voltage level required by the resolver "exciter". Its format is UFix16_11.

Outputs

SyncThis signal is the synchronization pulse train. It is connected to the ModelSync signal.
Theta_PU_[X] where X=[0,1]This output is the resolver calculated angle in per unit. It varies from 0 to 1 for angle positions from 0 to 2π with angle steps as accurate as 2.4e-5 radian. Its format is UFix18_18.
Carrier_PU_[X] where X=[0,1]This output is the carrier obtained by Resolver In block after rescaling in per unit. This signal is useful to calibrate Resolver In block. Its format is Fix18_14.
Sine_PU_[X] where X=[0,1]This output is the sine signal obtained by Resolver In block after rescaling in per unit. This signal is useful to calibrate Resolver In block. Its format is Fix18_14.
Cosine_PU_[X] where X=[0,1]

This output is the cosine signal obtained by Resolver In block after rescaling in per unit. This signal is useful to calibrate Resolver In block. Its format is Fix18_14.

InterSpeed_[X] where X=[0,1]

This output represents the difference of position in one CPU step. It is used to estimate the angular speed on the CPU side. Its format is UFix32_4.
CarrierUsedResolverIn_[X] where X=[0,1]This output is the external carrier to be sent to the resolver exciter through an analog output interface. Voltage and current specifications of the analog output board should match the resolver specifications in order to prevent any destruction of the materials. The low power amplifier can be used to adapt the voltage and current levels to the resolver needs. Its format is Fix16_11.

Characteristics and Limitations

This block has no special characteristics.

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