Block

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Description

This block implements the standard way to package 2 Resolver Out functionality blocks into the standardized I/O interface.

Parameters

This block has no parameters.

Inputs

OutputMode	This ports gives indication on the current mode (Single-ended or Differential) which is set through RT-LAB (in the CPU model when using S-Functions driver flow, unchangeable "Single-Ended" when using OPAL-RT board driver).
CarrierSelect[X] where X=[1,2]	Chooses between the internal carrier and external carrier coming from Analog In module. Its format is UFix1_0.
CarrierFreqIntegrationFactor[X] where X=[1,2]	Internal carrier frequency coming from the CPU model. Its format is UFix32_24. This input is a factor of the real value. The value at the input is the carrier frequency multiplied by 10x10^-9 (tsfpga) and 2^18 (integrator output maximum value).
CarrierAmp[X] where X=[1,2]	Internal carrier amplitude coming from the CPU model. Its format is Fix16_11.
SinAmp[X] where X=[1,2]	Amplitude (coming from CPU model) of the generated modulated sine signal. Its format is UFix16_11.
SinBias[X] where X=[1,2]	Bias (coming from CPU model) of the generated modulated sine signal. Its format is Fix16_11.
CosAmp[X] where X=[1,2]	Amplitude (coming from CPU model) of the generated modulated cosine signal. Its format is UFix16_11.
CosBias[X] where X=[1,2]	Bias (coming from CPU model) of the generated modulated cosine signal. Its format is Fix16_11.
SpeedIntegrationFactor[X] where X=[1,2]	Speed coming from the CPU model. Its format is Fix32_25. This input is a factor of the real value. The value at the input is the speed multiplied by 10x10^-9 (tsfpga) and 2^18 (integrator output maximum value).
Ext[X] where X=[1,2]	External carrier coming from Analog In module. Its format is Fix16_10.
Ch03	External sine coming from Analog In module. Its format is Fix18_16.
Ch07	External sine coming from Analog In module. Its format is Fix18_16.

Outputs

Ch01_Ch00	Set of signals for Resolver_1. Ch00: Carrier (either internal or external) used for modulated signals generation is the internal carrier frequency coming from CPU model. Its format is Fix16_11. Ch01: Resolver modulated sine. Its format is Fix16_11.
Ch03_Ch02	Set of signals for Resolver_1. Ch02: Resolver modulated cosine. Its format is Fix16_11. Ch03: External sine coming from Analog In module.
Ch05_Ch04	Set of signals for Resolver_2. Ch04: Carrier (either internal or external) used for modulated signals generation is the internal carrier frequency coming from CPU model. Its format is Fix16_11. Ch05: Resolver modulated sine. Its format is Fix16_11.
Ch07_Ch06	Set of signals for Resolver_1. Ch06: Resolver modulated cosine. Its format is Fix16_11. Ch07: External sine coming from Analog In module.

Characteristics and Limitations

This block has no specific characteristics or limitations.

RT-XSG Documentation

Resolver Output Subsection