Block

Mask

Description

This block implements the standard way to package 8 PWMO functionality blocks into the standardized I/O interface.

Parameters

This block has no parameters.

Inputs

RCO[X] where X=[0,7]	This signal is the duty cycle. Its should be inside the [0,1] range, although no limitation is set for this signal format. As an example, a UFixX_X format suits well the RCO signal (X=10 gives a 0.1% duty cycle precision).
Frequency[X] where X=[0,7]	This signal sets the PWM carrier frequency. The value should correspond to the proportion of the carrier period that equals one FPGA clock cycle. It is normal for this signal to be very small, and thus to use a very large bit-count numerical format. The recommended format is UFix42_42.
Polarity[X] where X=[0,7]	The value entered should be either a ‘0’ or a ‘1’. A ‘0’ for this input means that the signal is active-low, which means that a ‘Low’ output voltage is generated for a ‘1’ and a ‘High’ output voltage is generated for a ‘0’. A ‘1’ for this parameter means that the signal is active-high (default), which means that a ‘Low’ output voltage is generated for a ‘0’ and a ‘High’ output voltage is generated for a ‘1’.
DeadTime[X] where X=[0,3]	This signal sets the dead time between the two complementary phases of the PWM signal. It corresponds to an integer number of FPGA clock cycles in the [0, 1023] range.
Symm_mode[X] where X=[0,7]	This input sets the PWM generation pattern. This signal is 1-bit wide (‘0’ corresponding to the Asymmetric mode and ‘1’ to the Symmetric mode). If the generation mode is symmetric, the PWM carrier is a triangular waveform. An asymmetric generation mode corresponds to a sawtoothed carrier waveform. As a result, the symmetric PWM active phase is symmetric to the beginning of the PWM period while the asymmetric PWM active phase is asymmetric to the beginning of the PWM period.
InitPhase[X] where X=[0,7]	The initial phase of the carrier is expressed as a cycle ratio, between 0 and 1. It is quantized to the nearest 1/1000. Thus, numerical format UFix10_10 is recommended.
Sync	This signal is the synchronization signal. It is used to reset the carrier waveform generator phase to zero and to synchronize the Polarity, On/Off, Symm_mode and DeadTime inputs. The Sync input is generally managed by a PWMO Unpacking block, which extracts the Frequency and Sync inputs of all channels of a multiple-phase PWM generator array. This signal should be 1-bit wide.
Complementary	When high, this signals enables the output of the block to correspond to the complementary PWM waveform.

Outputs

HSOut	1-bit wide PWM signal.

Characteristics and Limitations

The Sync signal fed to this block should be sent synchronously with the beginning of a new PWM carrier period, as it resets the carrier generator to its initial phase. As a result, the most convenient way to generate the Sync input is via a Synchronization manager that sets the Sync and Frequency signals. Note that if no Sync signal is received, the PWM generation will continue perpetually, unless a Fault flag is received, and RCO will continue to be updated at each PWM period and/or mid-period.

One-shot PWM generation can be achieved by appropriate use of the On/Off signal.

RT-XSG Documentation

PWM Output Subsection