Block

Mask

This block recovers the data from RT-LAB through the DataIN and LoadIN blocks and generates the signals needed by an application block.

This block has no parameters.

DataIn	This signal must be connected to one of the DataINi output ports of the DataIn block.
DataINSOF	This signal must be connected to one of the SofINi output ports of the DataIn block.
LoadIn	This signal must be connected to one of the Cfg_INi input ports of the LoadIn block.
LoadInSOF	This signal must be connected to one of the SofINi input ports of the LoadIn block.

RCO[X] where X=[0,7]	This signal is the duty cycle. Its format is UFix10_0 (0.1% duty cycle precision).
Frequency[X] where X=[0,7]	This signal is the PWM carrier frequency. The value should correspond to the proportion of the carrier period that equals one FPGA clock cycle. It is normal for this signal to be very small, and thus to use a very large bit-count numerical format. Its format is UFix42_42.
Polarity[X] where X=[0,7]	This signal is the polarity. A value ‘0’ for this signal means that the PWM is active-low, while a value ‘1’ means that the PWM is active-high (default).
DeadTime[X] where X=[0,3]	This signal is the dead time between the two complementary phases of the PWM signal. It corresponds to an integer number of 10-ns clock cycles in the [0, 1023] range.
Symm_mode[X] where X=[0,7]	This signal is the PWM generation pattern. It is a 1-bit wide (‘0’ corresponding to the Asymmetric mode and ‘1’ to the Symmetric mode).
InitPhase[X] where X=[0,7]	This signal is the initial phase of the carrier, expressed as a cycle ratio, between 0 and 1. It is quantized to the nearest 1/1000. Its value is on 10 bits.
Sync	This signal is the synchronization signal, 1-bit wide.
Complementary	This signal is to select the PWM complementary output.

This Block has no specific characteristics or limitations.