Block

Mask

This block recovers the data from RT-LAB through the DataIN and LoadIN blocks and generates the signals needed by an application block.

This block has no parameters.

DataIn	This signal must be connected to one of the DataINi output ports of the DataIn block.
DataINSOF	This signal must be connected to one of the SofINi output ports of the DataIn block.
LoadIn	This signal must be connected to one of the Cfg_INi input ports of the LoadIn block.
LoadInSOF	This signal must be connected to one of the SofINi input ports of the LoadIn block.

OutputMode	This ports gives indication on the current mode (Single-ended or Differential) which is set through RT-LAB (in the CPU model when using S-Functions driver flow, unchangeable "Single-Ended" when using OPAL-RT board drivers)
CarrierSelect[X] where X=[1,2]	This port indicates a choice between the internal carrier and external carrier to be sent to Analog In module. Its format is UFix1_0.
CarrierFreqIntegrationFactor[X] where X=[1,2]	This port is the internal carrier frequency, coming from the CPU model. Its format is UFix32_24. It is a factor of the real value.
CarrierAmp[X] where X=[1,2]	This port is the internal carrier amplitude, coming from the CPU model. Its format is Fix16_11.
SinAmp[X] where X=[1,2]	This port is the amplitude, coming from CPU model, of the modulated sine signal to be generated. Its format is UFix16_11.
SinBias[X] where X=[1,2]	This port is the bias, coming from CPU model, of the modulated sine signal to be generated. Its format is Fix16_11.
CosAmp[X] where X=[1,2]	this port is the amplitude, coming from CPU model, of the modulated cosine signal to be generated. Its format is UFix16_11.
CosBias[X] where X=[1,2]	This port is the bias, coming from CPU model, of the modulated cosine signal to be generated. Its format is Fix16_11.
SpeedIntegrationFactor[X] where X=[1,2]	This port is the speed, coming from the CPU model. Its format is Fix32_25. It is a factor of the real value.

This Block has no specific characteristics or limitations.